The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB slave interface and so can be driven by software or ...

The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using ...